ArchSilc Intelligent Verification Infrastructure - AiVi
ArchSilc Intelligent Verification Infrastructure AiVi - built on SilcNet - enables accelerated development and deployment of advanced RTL verification environments. UNIFORM Simulation, Acceleration, and Emulation Testbench.
Verification Scalability
- Integration to C++, SystemC, RTL (Verilog, VHDL), and silicon prototype (acceleration, emulation, FPGA) environments
- Protocol Compliancy, Flow-Level, and Multi-Protocol interoperation Verification Automation
- API, DPI, and SCE-MI based Interfaces
- C++, HDL, HVL, and HVDL based test case creation
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