AiVi - PCI Express
ArchSilc's Intelligent Verification Infrastructure [AiVi] for PCI Express automates functional verification of PCI Express based systems. AiVi-PCI Express automates layer based PCI-SIG protocol compliancy validation and virtual CPU based driver verification for faster, complete functional verification.
PCI Express Protocol Stack Model Features:
- PCI Express Base Specification, Rev 1.1 Standard Compliant.
- Operation Modes: Endpoint, Root Complex, Switch and PCI-Express-PCI Bridge
- Layer based configuration for all Protocol Data Units (Application, TLP, DLLP and PHY)
- Configurable LINK width selection (1, 2, 4, 8, 12, 16 and 32)
- Automated TLP creation and ordering, TLP reply, LCRC, TLP sequence number, ACK/NACK, 8B/10B encoding/decoding, IDLE insertion.
- Exhaustive PCI Express compliancy test library
High-performance, synthesisable PHY and SCE-MI interface for hardware assisted functional verification (accelerator, emulator, FPGA prototype)