AiVi - Next Generation SONET
ArchSilc’s Intelligent Verification Infrastructure [AiVi] for next generation, SONET/SDH systems automates functional verification of SONET/SDH systems supporting data [e.g. IP, ATM, Ethernet] and storage [FibreChannel] traffic over legacy SONET/SDH systems. AiVi automates SONET/SDH and Ethernet protocol compliancy validation, GFP [Frame and Transparent] encapsulation, PPP/HDLC encapsulation, Virtual Concatenation [High and Low order], and LCAS. AiVi provides scalable verification environment that enables protocol focus verification at module, cluster and system level, and exhaustive verification reuse to meet time to market requirements.
Verification Scalability:
- Integration to C++, SystemC, RTL (Verilog, VHDL), and silicon prototype (acceleration, emulation, FPGA) environments through high performance, transaction level API
- System Verilog 3.1a DPI Standard Compliant
- Support for advanced Assertion based Verification & SQL analysis
Testcases Development & Proprietary Functional Analyzer:
- Advanced Configurable Elements based core technology enabling complex test case development in Verilog/VHDL, C, C++, SystemC, and Python, programming languages.
- Modular and layer based core architecture for proprietary feature implementation in user favorite programming languages [e.g. System Verilog, C/C++, SystemC]