ArchSilc’s vision is to Eliminate Verification Gap and enable faster, complete functional verification!
Functional verification continues to be the number one focus area for faster time-to-market. With unprecedented design IP reuse, it is easier to design systems and systems on chip (SoC) faster than to fully verify them prior to silicon commitment.

ArchSilc provides high-performance network simulator SilcNet and Intelligent Verification Infrastructure AiVi for exhaustive functional verification of convergent systems and SoC designs.

SilcNet and AiVi enables

  • Software Verification
  • RTL Verification
  • System-Level Verification



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